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Freescale Semiconductor, Inc.
JTAG
AC OPERATING CONDITIONS AND CHARACTERISTICS
FOR THE TEST ACCESS PORT (IEEE 1149.1)
(TJ < 120 ° C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 ? Termination to 1.5 V
C
R,
T
12 O
tCKH
UC 12
tCKL
D
ON
tA
M t
S
AL
SC
tSD
E
tSR
RE
F
tH
BY
tHD
tHR
D
VE
I –IR and SHIFT–DR state of the TAP state machine.
H
± C
3. Transition is measured R 500 mV from steady–state voltage. This parameter is sampled and not 100% tested.
TAP CONTROLLER TIMING
Clock High Time —
Clock Low Time —
Clock Low to Output Valid 5 9
I
Clock Low to Output High–Z tCKZ 0 9
Clock Low to Output Active E CKX 0 9
E
Setup Times: TMS tS 2 —
TDI 2
TRST 2
Hold Times: TMS 2 —
TDI 2
TRST 10
NOTES:
1. TDO will High–Z from a clock low edge depending on the current state of the TAP state machine.
2. TDO is active only in the SHIFT
A
tCKH
tCK
tCKL
TCK TEST
CLOCK
tH
tS
TMS TEST
MODE SELECT
tHD
tSD
TDI TEST
DATA IN
Cycle Time tCK 30 IN —
Parameter Symbol Min Max .
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
2, 3
TDO TEST
DATA OUT
TRST
tHR
tA
tSR
Figure 4. TAP Controller Timing
tCKZ
tCKX
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM69C432 ? SCM69C432
15
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